I'm giving a seminar on Friday...
May. 24th, 2004 04:27 pm![[personal profile]](https://www.dreamwidth.org/img/silk/identity/user.png){kind=small}
compilerbitchSubject: Hardware Partial Evaluation - CPRG meeting
Speaker: Sarah Thompson (CPRG)
Title: Bit-Level Partial Evaluation of Synchronous Circuits
Date: Fri 28 May
Time: 3-4pm
Place: FC22, WGB
Abstract:
Partial evaluation has been known for some time to be very effective when applied to software; in this paper we demonstrate that it is also of significant benefit when applied to hardware.
We present a bit-level algorithm that supports the partial evaluation of synchronous digital circuits. Full PE of combinational logic is noted to be equivalent to Boolean minimisation. A loop unrolling technique, supporting both partial and full unrolling, is described. Experimental results are given, showing that partial evaluation of a simple microprocessor against a ROM image is equivalent to compiling the ROM program directly into low level hardware.
Any cam-types with a vague interest of seeing me bounce up and down in front of a whiteboard are cordially invited...
Speaker: Sarah Thompson (CPRG)
Title: Bit-Level Partial Evaluation of Synchronous Circuits
Date: Fri 28 May
Time: 3-4pm
Place: FC22, WGB
Abstract:
Partial evaluation has been known for some time to be very effective when applied to software; in this paper we demonstrate that it is also of significant benefit when applied to hardware.
We present a bit-level algorithm that supports the partial evaluation of synchronous digital circuits. Full PE of combinational logic is noted to be equivalent to Boolean minimisation. A loop unrolling technique, supporting both partial and full unrolling, is described. Experimental results are given, showing that partial evaluation of a simple microprocessor against a ROM image is equivalent to compiling the ROM program directly into low level hardware.
Any cam-types with a vague interest of seeing me bounce up and down in front of a whiteboard are cordially invited...