At last... LaTeX inside Dot inside LaTeX

[compilerbitch]

I managed to get dot to draw a diagram where the boxes contained LaTeX formulae today:



A Haas diagram showing the lattice of values of my 15-value logic with respect to subset membership

The trick was to fire up LaTeX once for each bubble, with only the content of the bubble on the page (i.e. no headings/page numbers/etc.), then to use dvips -E to generate EPS with a tight bounding box. Getting dot to use these images was easy -- for each node, set the shape to epsf and specify the relevant EPS file. I then made dot export the whole diagram as an EPS, which allowed me to integrate it into a big LaTeX document. (As a slight aside, the whole document, diagrams and all is built by a single 500 line ML program).

I am such a geek. Someone slap me.

Comments

[fluffymark]

Oh wow. yes. Your diagram makes sense now. Apart from the meanings of S and C, I think I can follow it.

Re:

[compilerbitch.livejournal.com]

S = static, i.e. the value might be steady state true or steady state false, but it never transitions.

C = clean, i.e. the value might be clean false, true, up or down, but may never be dirty.

These values are a bit experimental, quite a recent idea actually. They can handle two important classes of signal that happen in real circuits, specifically signals that are unknown at design time but unchanging at run time (e.g. the contents of flash memory configuration, etc.), and signals that must be clean, such as clocks in synchronous circuits or pretty much anything in asynchronous circuits.

Re:

[fluffymark]

I must have been thinking about that diagram in my sleep, as I woke up realising that S meant static and C meant clean.

Re:

[compilerbitch.livejournal.com]

You can kind-of figure it out from the diagram, but well done for spotting it!

I'm planning to add a bunch of other operators that can't be defined directly in conventional logics, e.g. D-type flip flops, SR latches, C elements, etc. so I can have a go at deriving algebraic laws for manipulating circuits that contain them. I'm also planning on having a go at embedding these logics in a more sophisticated dense continuous time interval temporal logic for model checking purposes. It's fun so far...!