compilerbitch: That's me, that is! (Default)
[personal profile] compilerbitch
Looks like I'm going to be giving a proper for-real Cambridge undergrad lecture!

December 3rd, 10am, in the big lecture theatre in the William Gates Building, to all of the Part 1B Computer Design course (about 120 people). The subject is going to be reconfigurable computing -- i.e. using hardware compilation and FPGAs to build cut price supercomputers that have an entirely non-Von Neumann architecture. Obviously, the subject is very close to my heart, and getting to do some real lecturing as a PhD student, especially this soon after starting here, is a really big thing for me.

So, *superdupermegabounce*

Happy Sarah. This has cheered me up a lot, especially after the wobble I had at the weekend over the allergy/arthritis/not being able to go and see people thing.

(no subject)

Date: 2003-11-04 01:45 pm (UTC)
From: [identity profile] yvesilena.livejournal.com
RAH RAH RAH! GO SARAH! *hugs*

(no subject)

Date: 2003-11-04 04:25 pm (UTC)

(no subject)

Date: 2003-11-04 04:22 pm (UTC)
fluffymark: (Default)
From: [personal profile] fluffymark
*bounce*

Go you! :)

(no subject)

Date: 2003-11-04 04:26 pm (UTC)
From: [identity profile] compilerbitch.livejournal.com
Thanks!

PS: Good luck in Chicago!

(no subject)

Date: 2003-11-05 06:20 am (UTC)
From: [identity profile] fatdog.livejournal.com
cool. the first of many i'm sure.

(no subject)

Date: 2003-11-05 06:50 am (UTC)
From: [identity profile] compilerbitch.livejournal.com
*crosses fingers*

(no subject)

Date: 2003-11-06 01:59 am (UTC)
From: [identity profile] emomisy.livejournal.com
Cool.
And that sounds like an interesting lecture. It might have got me to actually go to lectures...

I like your layout BTW :-)

(no subject)

Date: 2003-11-06 03:44 am (UTC)
From: [identity profile] compilerbitch.livejournal.com
Most of that course seems pretty good -- it was heavily revamped for this year. The lab sessions are killing the less hardcore of the students -- they get to build their own Rugby clock receiver in an FPGA that has an ARM core on the silicon -- but it is all very cool. They get to use Verilog for the hardware and ARM assembler for their embedded firmware.

Oh, and thanks for the layout compliment! :-)

(no subject)

Date: 2003-11-07 04:21 am (UTC)
From: [identity profile] doseybat.livejournal.com
*hugs*
*waves*
*morehugs*
dont like the old job much, after all. pleased i am not continuing. annoying i cant phone..

(no subject)

Date: 2003-11-07 04:41 am (UTC)
From: [identity profile] compilerbitch.livejournal.com
{{{{ hugs, tea and virtual sympathy }}}}

I'll be around here at Eds during your couple of hours back at the Penguin house this afternoon, so feel free to call if you want to chat. Actually, I'll be working from college most of the day because the screen on my machine in the lab is a bit small -- hacking the LaTeX for my paper is much easier and quicker here, so I'm up for a call more or less any time you like.

(no subject)

Date: 2003-11-09 02:49 am (UTC)
From: [identity profile] davefish.livejournal.com
Ooh, thats really quite an exciting topic. I didn't realise that you were doing such interesting research.

(no subject)

Date: 2003-11-09 06:15 am (UTC)
From: [identity profile] compilerbitch.livejournal.com
Building supercomputers out of FPGAs is something I'm interested in, have been for years really. It's not actually my PhD project though -- I'm actually working on techniques that will allow very large chips to be designed and validated. This is actually, if a bit less sexy sounding, much more important. Current tools have just about hit their limit, and aren't really doing a good job of handling the bigger designs that are currently being contemplated by chip companies. It's not so much the designing as the getting right that's the problem -- to build a custom chip costs about $2 million, and if you get it wrong and need another try it will cost the same again. And again. So you have to get it right first time -- what I'm working on is some new theory that will allow tools to be created that can identify whole categories of problem by static analysis, so the chip doesn't need to be built or even simulated.

Looks interesting so far -- hopefully the first paper will go into Designing Correct Circuits in Barcelona next spring.

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