compilerbitch (![[personal profile]](https://www.dreamwidth.org/img/silk/identity/user.png)
compilerbitch) wrote2003-05-25 10:02 am
compilerbitch) wrote2003-05-25 10:02 am
PhD news -- interest from MIT
One of the people I sent a funding begging letter to was Arvind at Sandburst Inc. They couldn't give me any money, but the interesting thing is that Arvind's sabbatical is now over, so he's back at MIT and is running their computation structures group.
It seems that MIT are interested in possible collaboration on my area of research.
In 1991, I proposed my own M.Sc research project. I'd had the idea that it should be possible to compile software into hardware, making it possible to design hardware more or less as easily as it is to write software. I wrote a hardware compiler (not actually the first ever, but I didn't know that at the time). It worked very well, I got my master's and a distinction for my thesis.
Since this was pre-Internet era, I was limited to the (not that good) uni library. They had literally nothing of use, so I ended up having to invent all of the underlying algorithms from scratch. Whilst the front end of the compiler was fairly conventional, it's code generation approach had to be thought up from scratch. To this day, no one else has built a hardware compiler that quite works like it, but I've since found that I'd reinvented (pre-invented in some cases!) a few other things I'd not heard of, especially partial evaluation and an intermediate compiler representation that has since become known as gated static single assignment form (aka Gated SSA).
My compiler wasn't perfect -- it had no support for scheduling, and was specifically designed to generate hardware that effectively ran the entire program in a single clock cycle (this is what I've subsequently named Single Cycle Hardware Compilation, or SCHC for short). It was, however, as best I can tell the first ever hardware compiler to heavily use partial evaluation (aka PE). It seems to have been sufficiently ahead of its time (or at least sufficiently obscure, if I'm in a pessimistic mood) that a PhD proposal based on taking the idea further is still regarded as interesting.
Until recently, the only other group I knew of that had done some hardware PE was at Glasgow, and relatively lightweight. They were using PE to rapidly specialise already-routed chip layouts. This was interesting in its own right, but quite different to the idea of using it at a fundamental level within the compilation/synthesis of the design in the first place.
Now, it seems, that MIT and the spinoff company Sandburst have been working for a while now on a hardware compiler called Bluespec that heavily uses PE internally, although they haven't published any papers yet that describe this in any detail. It is still different to my approach, in that Bluespec works at a higher level than my compiler, transforming its Haskell-like source language into a term rewriting system (TRS), then using PE to optimise that into a form that can be mapped directly to the Verilog language and thence passed on to an existing commercial logic synthesis/chip layout system. This is again not the same as my approach, but is very interesting in its own right.
Anyway, enough of the background, back to the story. My PhD supervisor and Prof. Arvind at MIT have started talking about possible collaboration. This is clearly good news for me, because suddenly I've gone from being largely alone in thinking that hardware PE is a good idea to having that idea independently supported by another (major) research group. It probably also means that I'll get to spend some time at MIT myself.
This is looking good!
If you're interested, my PhD proposal is here.
There's a longer document that serves the same purpose, but includes more technical background, so is more suitable for non-experts:
hpe.ps.gz
And if you're *really* interested, here's a paper on the single-cycle hardware compilation algorithm I developed for my M.Sc thesis project in 1991 that forms the theoretical basis for my PhD proposal:
schc2.ps.gz
I have PDF versions of the last two documents, but they are not currently on my web site. Let me know if you want that version and I'll email them to you.
It seems that MIT are interested in possible collaboration on my area of research.
In 1991, I proposed my own M.Sc research project. I'd had the idea that it should be possible to compile software into hardware, making it possible to design hardware more or less as easily as it is to write software. I wrote a hardware compiler (not actually the first ever, but I didn't know that at the time). It worked very well, I got my master's and a distinction for my thesis.
Since this was pre-Internet era, I was limited to the (not that good) uni library. They had literally nothing of use, so I ended up having to invent all of the underlying algorithms from scratch. Whilst the front end of the compiler was fairly conventional, it's code generation approach had to be thought up from scratch. To this day, no one else has built a hardware compiler that quite works like it, but I've since found that I'd reinvented (pre-invented in some cases!) a few other things I'd not heard of, especially partial evaluation and an intermediate compiler representation that has since become known as gated static single assignment form (aka Gated SSA).
My compiler wasn't perfect -- it had no support for scheduling, and was specifically designed to generate hardware that effectively ran the entire program in a single clock cycle (this is what I've subsequently named Single Cycle Hardware Compilation, or SCHC for short). It was, however, as best I can tell the first ever hardware compiler to heavily use partial evaluation (aka PE). It seems to have been sufficiently ahead of its time (or at least sufficiently obscure, if I'm in a pessimistic mood) that a PhD proposal based on taking the idea further is still regarded as interesting.
Until recently, the only other group I knew of that had done some hardware PE was at Glasgow, and relatively lightweight. They were using PE to rapidly specialise already-routed chip layouts. This was interesting in its own right, but quite different to the idea of using it at a fundamental level within the compilation/synthesis of the design in the first place.
Now, it seems, that MIT and the spinoff company Sandburst have been working for a while now on a hardware compiler called Bluespec that heavily uses PE internally, although they haven't published any papers yet that describe this in any detail. It is still different to my approach, in that Bluespec works at a higher level than my compiler, transforming its Haskell-like source language into a term rewriting system (TRS), then using PE to optimise that into a form that can be mapped directly to the Verilog language and thence passed on to an existing commercial logic synthesis/chip layout system. This is again not the same as my approach, but is very interesting in its own right.
Anyway, enough of the background, back to the story. My PhD supervisor and Prof. Arvind at MIT have started talking about possible collaboration. This is clearly good news for me, because suddenly I've gone from being largely alone in thinking that hardware PE is a good idea to having that idea independently supported by another (major) research group. It probably also means that I'll get to spend some time at MIT myself.
This is looking good!
If you're interested, my PhD proposal is here.
There's a longer document that serves the same purpose, but includes more technical background, so is more suitable for non-experts:
hpe.ps.gz
And if you're *really* interested, here's a paper on the single-cycle hardware compilation algorithm I developed for my M.Sc thesis project in 1991 that forms the theoretical basis for my PhD proposal:
schc2.ps.gz
I have PDF versions of the last two documents, but they are not currently on my web site. Let me know if you want that version and I'll email them to you.